Device interconnections in Very Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated (ULSI) semiconductor devices or chips typically have multilevel structures containing patterns of metal wiring layers encapsulated in an insulator. Wiring structures within a given level of wiring are separated by an intra level dielectric, while the individual wiring levels are separated from each other by layers of an inter level dielectric. Conductive vias are formed in the inter level dielectric to provide inter level contacts between the wiring traces.
The scaling of 2D devices faces challenges such as integration of different chip functionalities required in advanced processor systems. Industry is looking to 3D integration (3DI) of devices to achieve these ends. One element needed in 3DI schemes comprises through substrate (usually Si) via connections to enable connection between device layers as well as input/output (I/O) connection to the external components. Prior art processes describe etching deep (about 20 micron to about 150 micron) through Si vias filled with tungsten or copper as a means to enable these connections. These vias are difficult to fabricate in the traditional complementary metal oxide semiconductor (CMOS) fabrication environment and present cost and reliability issues. Alignment of patterns required on the bonded and thinned wafer assembly often requires the use of alignment marks produced using the same deep silicon etch and fill process concurrently with the through via formation. Such marks are not easy to produce with good fidelity and as such are not very conducive for reliable litho alignment. In the present invention we present an alternative way to achieve through device layer via connections by taking advantage of the use of silicon-on-insulator (SOI) substrates.
Industry experienced problems in standard through joining and face-to-face joining 3DI. Some of these problems include expensive deep Si via etch and fill processing which is difficult to extend not only to smaller dimensions in the device but also devices having high aspect ratios.
Additionally, front-to-back alignment for post-thinning lithography is limited by the quality of the marks formed by deep thru Si filled vias in the process. Also, topography of the back side of the device after thinning (W and/or Si) can be high and may not be easy to planarize.
One attempt to overcome these and other related problems comprises a so-called via plus riveting approach to 3DI which eliminates deep Si vias but requires etching through the back end of the line (BEOL), middle of the line (MOL), and front end of the line (FEOL) dielectric layers after the device is fully built. This is an alternate approach that will allow formation of Cu thru vias.